DM74LS73A Datasheet - Fairchild Semiconductor

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

DM74LS73A General Description

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the neg.

DM74LS73A Datasheet (53.28 KB)

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DM74LS73A

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Fairchild Semiconductor

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53.28 KB

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Dual negative-edge-triggered master-slave j-k flip-flops.
DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dua.

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DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops Fairchild Semiconductor

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DM74LS73A General Description

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