HD74CDC2510B
Overview
- Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” Phase-lock loop clock distribution for synchronous DRAM applications External feedback (FBIN) pin is used to synchronize the outputs to the clock input No external RC network required Support spread spectrum clock (SSC) synthesizers Only by a change of a suffix (A to B) for standardization, there isn’t any change of the product. Note:
