HD74CDC2510B driver equivalent, 3.3-v phase-lock loop clock driver.
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* Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” Phase-lock loop clock distribution for synchronous DRAM applications Exte.
External feedback (FBIN) pin is used to synchronize the outputs to the clock input No external RC network required Suppo.
The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifical.
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