HD74CDCF2510B Datasheet PDF (3.3-V Phase-lock Loop Clock Driver)

HD74CDCF2510B - 3.3-V Phase-lock Loop Clock Driver

Description

The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver.

It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Datasheet Details

Part number	HD74CDCF2510B
Manufacturer	Renesas
File Size	216.00 KB
Description	3.3-V Phase-lock Loop Clock Driver
Datasheet	HD74CDCF2510B Datasheet
Additional preview pages of the HD74CDCF2510B datasheet.

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Full PDF Text Transcription

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HD74CDCF2510B 140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver REJ03D0828-1000 (Previous: ADE-205-225H) Rev.10.00 Apr 07, 2006 Description The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDCF2510B operates at 3.3 V VCC and is designed to drive up to five clock loads per output. Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.

Published: Dec 4, 2017 |