HD74HC114 Datasheet | Hitachi Semiconductor

Dual J-K Flip-Flops (with Preset, mon Clear and mon Clock) Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops are controlled by a mon clear and a mon clock. Preset and clear are independent of the clock and acplished by a low logic level on the corresponding input. Features - - - - - High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static)...