HD74HC112 Datasheet PDF - Hitachi Semiconductor Dual J-K Flip-Flops Specs

HD74HC112 - Dual J-K Flip-Flops

Datasheet Summary

Description

Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs.

This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.

Features

High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Preset L H L H H H H H H H Note: Clear H L L H H H H H H H L H Clock X X X J X X X L L H H X X X K X X X L H L H X X X Output Q H L H.
1 Q L H H.
1 No Change L H Toggle No Cha.

Datasheet Details

Part number	HD74HC112
Manufacturer	Hitachi Semiconductor
File Size	60.23 KB
Description	Dual J-K Flip-Flops
Datasheet	HD74HC112 Datasheet
Additional preview pages of the HD74HC112 datasheet.

📁 Similar Datasheet

HD74HC112 - Dual J-K Flip-Flops (Renesas)

HD74HC11 - Triple 3-input AND Gates (Renesas)

HD74HC113 - Dual J-K Flip-Flops (Renesas)

HD74HC10 - Triple 3-input NAND Gates (Renesas)

HD74HC107 - Dual J-K Flip-Flops (Renesas)

HD74HC108 - Dual J-K Flip-Flops (Renesas)

HD74HC109 - Dual J-K Flip-Flops (Renesas)

HD74HC123A - Dual Retriggerable Monostable Multivibrators (Renesas)

HD74HC125 - Quad. Bus Buffer Gates (Renesas)

HD74HC126 - Quad. Bus Buffer Gates (Renesas)

Full PDF Text Transcription

Click to expand full text

HD74HC112 Dual J-K Flip-Flops (with Preset and Clear) Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input.

Published: Mar 23, 2005 |