Datasheet4U Logo Datasheet4U.com

HD74HC137 - 3-to-8-line Decoder/Demultiplexer

Datasheet Summary

Description

The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs.

When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches.

As long as GL remains high no address changes will be recognized.

Features

  • High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 10 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 V to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta.

📥 Download Datasheet

Datasheet preview – HD74HC137

Datasheet Details

Part number HD74HC137
Manufacturer Renesas
File Size 267.51 KB
Description 3-to-8-line Decoder/Demultiplexer
Datasheet download datasheet HD74HC137 Datasheet
Additional preview pages of the HD74HC137 datasheet.

📁 Similar Datasheet

  • HD74HC137 - 3-to-8-line Decoder/Demultiplexer (Hitachi Semiconductor)
  • HD74HC131 - 3-to-8-line Decoder/Demultiplexer (Hitachi Semiconductor)
  • HD74HC132 - Quad. 2-input NAND Schmitt Triggers (Hitachi Semiconductor)
  • HD74HC133 - 13-input NAND Gate (Hitachi Semiconductor)
  • HD74HC138 - 3-to-8-line Decoder/Demultiplexer (Hitachi Semiconductor)
  • HD74HC139 - Dual 2-to-4-line Decoders/Demultiplexers (Hitachi Semiconductor)
  • HD74HC10 - Triple 3-input NAND Gates (Hitachi Semiconductor)
  • HD74HC107 - Dual J-K Flip-Flops (Hitachi Semiconductor)
  • HD74HC108 - Dual J-K Flip-Flops (Hitachi Semiconductor)
  • HD74HC109 - Dual J-K Flip-Flops (Hitachi Semiconductor)
Other Datasheets by Renesas

Full PDF Text Transcription

Click to expand full text
HD74HC137 3-to-8-line Decoder/Demultiplexer with Address Latch REJ03D0569-0200 (Previous ADE-205-443) Rev.2.00 Oct 11, 2005 Description The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HC137 is ideally suited for the implementation of glitchfree decoders in stored-address applications in bus oriented systems. Features • High Speed Operation: tpd (A, B, C to Y) = 16.
Published: |