HD74HC112

Dual J-K Flip-Flops

Renesas

HD74HC112 Features

* High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF)

* High Output Current: Fanout of 10 LSTTL Loads

* Wide Operating Voltage: VCC = 2 to 6 V

* Low Input Current: 1 µA max

* Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)

HD74HC112 General Description

Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the c.

HD74HC112 Datasheet (204.07 KB)