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HD74HC112 - Dual J-K Flip-Flops

Datasheet Summary

Description

Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs.

This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.

Features

  • High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 10 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC112P DILP-16 pin PRDP0016AE-B (DP-16FV) P HD74HC112FPEL SOP-16 pin (JEITA) PRSP0016DH-.

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Datasheet Details

Part number HD74HC112
Manufacturer Renesas
File Size 204.07 KB
Description Dual J-K Flip-Flops
Datasheet download datasheet HD74HC112 Datasheet
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Full PDF Text Transcription

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HD74HC112 Dual J-K Flip-Flops (with Preset and Clear) REJ03D0562-0200 (Previous ADE-205-435) Rev.2.00 Oct 11, 2005 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input.
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