H5TQ4G63CFR-xxI Datasheet | SK Hynix

4Gb DDR3 SDRAM 4Gb DDR3 SDRAM Lead-Free&Halogen-Free (Ro HS pliant) H5TQ4G83CFR-xx C H5TQ4G83CFR-xx I H5TQ4G83CFR-xx L H5TQ4G83CFR-xx J H5TQ4G63CFR-xx C H5TQ4G63CFR-xx I H5TQ4G63CFR-xx L H5TQ4G63CFR-xx J - SK Hynix reserves the right to change products or specifications without notice. Rev. 1.3/ June 2015 Revision History Revision No. 0.1 0.2 0.3 0.4 1.0 1.1 1.2 1.3 History Initial Version PKG Dimensions Update Operating Frequency Modify Input/Output Capacitance Tyop Correct Official Datasheet with IDD Spec PKG Dimension Correct PKG Dimension Correct PKG Dimension Correct (INDEX MARK) Draft Date Feb. 2014 Apr. 2014 July. 2014 July. 2014 Oct. 2014 Dec. 2014 Mar. 2015 Jun. 2015 Remark Page 32,33 Page 4, Note1 Page 25 Page 24 Page 33 Page 32,33 Page 32 Rev. 1.3/ June 2015 Description The H5TQ4G83CFR-xx C,H5TQ4G63CFR-xx C, H5TQ4G83CFR-xx I, H5TQ4G63CFR-xx I, H5TQ4G83CFR-xx L, H5TQ4G63CFR-xx L,H5TQ4G83CFR-xx J and H5TQ4G63CFR-xx J are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. SK Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information Features - VDD=VDDQ=1.5V +/- 0.075V - Fully differential clock inputs (CK, CK) operation - Differential Data Strobe (DQS, DQS) - On chip DLL align DQ, DQS and DQS transition with CK transition - DM masks write data-in at the both rising and falling edges of the data strobe - All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock - Programmable CAS...