HY5DU281622FTP
Description
The HY5DU281622FT(P) is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. This Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
Key Features
- VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333) VDD, VDDQ = 2.4V min ~ 2.7V max (Typical 2.6V Operation +0.1/- 0.2V for DDR400 and 400Mbps/pin product) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) * * * * * *
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 2/2.5 (DDR266, 333) and 3 (DDR400 and 400Mbps/pin product) supported Programmable burst length 2/4/8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported tRAS lock out function supported 4096 refresh cycles/64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Lead free (*ROHS Compliant) * * * * * * *
- DM mask write data-in at the both rising and falling edges of the data strobe
