HY5DU281622LT
description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/May. 02 1
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HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T
Revision History
1. Revision 0.2 (Nov.01) 1) Device operation and timing diagram removed 2) t HZ / t LZ SPEC defined 2. Revision 0.3 (Feb.02) 1) “Preliminary” removed 3. Revision 0.4 (May. 02) 1) Input leakage current changed from +/-5u A to +/-2u A
Rev. 0.4/May. 02
HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T DESCRIPTION
The Hynix HY5DU28422A(L)T and HY5DU28822A(L)T and HY5DU281622A(L)T are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising...
