ICSSSTUA32S869B buffer equivalent, 14-bit configurable registered buffer.
* 14-bit 1:2 registered buffer with parity check functionality
* Supports SSTL_18 JEDEC specification on data inputs and outputs
* 50% more dynamic driver st.
The ICSSSTUA32S869B is 14-bit 1:2 registered buffer with parity is designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS driv.
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