ICSSSTUB32871A - 27-Bit Registered Buffer

Product Overview

ICS

Part number	ICSSSTUB32871A
Manufacturer	ICS
File Size	228.67 KB
Description	27-Bit Registered Buffer
Datasheet	ICSSSTUB32871A Datasheet
Additional preview pages of the ICSSSTUB32871A datasheet.

This 27-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

27-bit 1:1 registered buffer with parity check functionality.
Supports SSTL_18 JEDEC specification on data inputs and outputs.
Supports LVCMOS switching levels on RESET input.
50% more dynamic driver strength than standard SSTU32864.
Low voltage operation VDD = 1.7V to 1.9V.
Available in 96 BGA package Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 96 Ball BGA (Top View) Functionality Truth Table In puts RESET H H H H H H.

📁 Similar Datasheet

ICSSSTU32866 - 25-Bit Configurable Registered Buffer (Integrated Circuit System)
ICSSSTUAF32865A - 25-BIT CONFIGURABLE REGISTERED BUFFER (IDT)
ICSSSTUAF32866B - 25-BIT CONFIGURABLE REGISTERED BUFFER (IDT)
ICSSSTUAF32866C - 25-BIT CONFIGURABLE REGISTERED BUFFER (IDT)
ICSSSTUAF32868A - 28-BIT CONFIGURABLE REGISTERED BUFFER (IDT)
ICSSSTUAF32868B - 28-BIT CONFIGURABLE REGISTERED BUFFER (IDT)
ICSSSTUAF32869A - 14-BIT CONFIGURABLE REGISTERED BUFFER (IDT)
ICSSSTUAH32865A - 25-BIT CONFIGURABLE REGISTERED BUFFER (IDT)

Other Datasheets by ICS

Published: Oct 2, 2007 |