ICSSSTUB32871A Description
This 27-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are patible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS.
ICSSSTUB32871A Key Features
- 27-bit 1:1 registered buffer with parity check functionality
- Supports SSTL_18 JEDEC specification on data inputs and outputs
- Supports LVCMOS switching levels on RESET input
- 50% more dynamic driver strength than standard SSTU32864
- Low voltage operation VDD = 1.7V to 1.9V
- Available in 96 BGA package