ICS ICSSSTU32864
the ICSSSTU32864 must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS# and CSR# inputs and will gate the Qn outputs from changing states when both DCS# and CSR# inputs are high. The RST input has priority over the DCS# and CSR# control and will force the outputs low.| Part No. | ICSSSTU32864 |
|---|---|
| Datasheet | ICSSSTU32864 Download |
| Manufacturer |  ICS |
| Description | 25-Bit Configurable Registered Buffer |
| Buy | Stock & Price |
FEATURES
:● 25-bit 1:1 or 14-bit 1:2 configurable registered buffer
● Supports SSTL_18 JEDEC specification on data inputs and outputs
● Supports LVCMOS switching levels on CSR# and RESET# inputs
● Low voltage operation VDD = 1.7V to 1.9V
● Available in 96 BGA package Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 96 Ball BGA (Top View) Truth Table I nputs RST# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H X or Floating CSR# L L L H H H L L L H H H X or Floating L or H X or Floating L or H X or Floating L or H L or H L or H L or H L or H L or H CK CK# Dn, DODT, DCK E L H X L H X L H X L H X X or Floating Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# L L Q0 L L Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L Ball Assignments A DCKE B D2 C D3 D DODT E D5 NC D15 D16 NC D17 D18 RST# DCS# CSR# D19 D20 D21 D22 D23 D24 D25 V REF GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD V REF V DD GND V DD GND V DD GND V DD GND V DD GND V DD GND V DD G...
