Datasheet Details
| Part number | ICSSSTU32864 |
|---|---|
| Manufacturer | ICS |
| File Size | 140.58 KB |
| Description | 25-Bit Configurable Registered Buffer |
| Datasheet |
 ICSSSTU32864 Datasheet
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General Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18.
The control inputs are LVCMOS.
Key Features
- 25-bit 1:1 or 14-bit 1:2 configurable registered buffer.
- Supports SSTL_18 JEDEC specification on data inputs and outputs.
- Supports LVCMOS switching levels on CSR# and RESET# inputs.
- Low voltage operation VDD = 1.7V to 1.9V.
- Available in 96 BGA package Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 96 Ball BGA (Top View) Truth Table I nputs RST# H H H H H H H H H H H H L DCS# L L L L L L H H H H H H X or Floating CSR# L L L H H H L L.