ICSSSTUB32866B Datasheet | ICS

.. Integrated Circuit Systems, Inc. ICSSSTUB32866B Advance Information 25-Bit Configurable Registered Buffer for DDR2 Remended Application: - DDR2 Memory Modules - Provides plete DDR DIMM solution with ICS97ULP877 - Ideal for DDR2 400,533,667 and 800 Product Features : - 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality - Supports SSTL_18 JEDEC specification on data inputs and outputs - Supports LVCMOS switching levels on CSR and RESET inputs - Low voltage operation VDD = 1.7V to 1.9V - Available in 96 BGA package - Drop-in replacement for ICSSSTUA32864 - Green packages available Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 Functionality Truth Table Inputs RST H H H H H H H H H H H H L DCS CSR Dn, DODT, DCKE ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X ↑ ↓ L ↑ ↓ H L or H L or H X X or X or X or Floating Floating Floating CK CK Outputs, QCS L L Q0 L L Q0 H H Q0 H H Q0 L 96 Ball BGA (Top View) Qn L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L L L L L L L L H L H L H H L H L H L H H H H H H X or X or Floating Floating 1165- 10/25/06 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. ICSSSTUB32866B Advance Information Ball Assignments 25 bit 1:1 Register A B C D E F G H J K L M N P R T DCKE D2 D3 DODT D5 D6 PAR_IN CK CK D8 D9 D10 D11 D12 D13 D14 PPO D15 D16 QERR D17 D18 RST DCS CSR D19 D20 D21 D22 D23 D24 D25 VREF GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VREF VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD VDD QCKE Q2 Q3 QODT Q5 Q6 C1 QCS ZOH Q8 Q9 Q10 Q11 Q12 Q13 Q14 NC Q15 Q16 NC Q17 Q18 C0 NC ZOL Q19 Q20 Q21 Q22 Q23 Q24...