* 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality
* Supports SSTL_18 JEDEC specification on data inputs and outputs
*.

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers.

ICSSSTUB32864A

ICSSSTUB32871A

ICSSSTUB32872A

ICSSSTUBF32866A

ICSSSTU32864

ICSSSTU32866

ICSSSTUA32S869B

ICSSSTUAF32865A

ICSSSTUAF32866B

ICSSSTUAF32866C

ICSSSTUAF32868A

ICSSSTUAF32868B

ICSSSTUAF32869A