ICSSSTUB32866B Datasheet - ICS

25-Bit Configurable Registered Buffer

ICSSSTUB32866B Features

* 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* Supports LVCMOS switching levels on CSR and RESET inputs

* Low voltage operation VDD = 1.7V to 1.9V

ICSSSTUB32866B General Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM.

ICSSSTUB32866B Datasheet (569.97 KB)

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Datasheet Details

Part number:

ICSSSTUB32866B

Manufacturer:

ICS

File Size:

569.97 KB

Description:

25-bit configurable registered buffer.
www.DataSheet4U.com Integrated Circuit Systems, Inc. ICSSSTUB32866B Advance Information 25-Bit Configurable Registered Buffer for DDR2 Recommended .

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ICSSSTUB32866B 25-Bit Configurable Registered Buffer ICS

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ICSSSTUB32866B Features

ICSSSTUB32866B General Description

Datasheet Details

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