27-bit registered buffer.
* 27-bit 1:1 registered buffer with parity check functionality
* Supports SSTL_18 JEDEC specification on data inputs and outputs
* Supports LVCMOS switching .
This 27-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been o.
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