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ICSSSTUB32871A Datasheet Preview

ICSSSTUB32871A Datasheet

27-Bit Registered Buffer

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Integrated
Circuit
Systems, Inc.
ICSSSTUB32871A
27-Bit Registered Buffer for DDR2
Recommended Application:
Pin Configuration
• DDR2 Memory Modules
• Provides complete DDR DIMM solution with
ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A
123456
A
• Optimized for DDR2 400/533/667 JEDEC 4 Rank
VLP DIMMS
B
C
D
Product Features:
• 27-bit 1:1 registered buffer with parity check
functionality
• Supports SSTL_18 JEDEC specification on data
inputs and outputs
• Supports LVCMOS switching levels on RESET input
• 50% more dynamic driver strength than standard
SSTU32864
• Low voltage operation
VDD = 1.7V to 1.9V
• Available in 96 BGA package
E
F
G
H
J
K
L
M
N
P
R
T
96 Ball BGA
(Top View)
Functionality Truth Table
In puts
Outputs
RESET
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
DCS0
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
X or
floating
DCS1
L
L
L
H
H
H
L
L
L
H
H
H
H
H
H
X or
floating
CSGate
Enable
CK
X
X
X
X
X
X
X
X
X
L
L
L
H
H
H
X or
floating
L or H
L or H
L or H
L or H
L or H
X or
floating
Dn,
CK DODTn,
DCK En
L
H
L or H
X
L
H
L or H
X
L
H
L or H
X
L
H
L or H
X
L or H
L
H
X
X or X or
floating floating
Qn
L
H
Q0
L
H
Q0
L
H
Q0
L
H
Q0
Q0
Q0
Q0
L
QCS
QODT,
QCKE
LL
LH
Q0 Q0
LL
LH
Q0 Q0
HL
HH
Q0 Q0
HL
HH
Q0 Q0
HL
HH
Q0 Q0
LL
1186G—04/16/07




ICS

ICSSSTUB32871A Datasheet Preview

ICSSSTUB32871A Datasheet

27-Bit Registered Buffer

No Preview Available !

ICSSSTUB32871A
Ball Assignments
27 bit 1:1 Register
A DCKE0 D0
B DCKE1 D1
V REF
GND
VDD
GND
C D2
DODT1 VDD
VDD
D DODT0 PTYERR GND GND
E D3
D4
VDD
VDD
F D5 D6 GND GND
G PAR_IN RESET VDD
H CK
DCS0 GND
VDD
GND
J CK
K D7
DCS1 VDD
D8 GND
VDD
GND
L D9
D10
VDD
VDD
M D11 D12 GND GND
N D13 D14 VDD VDD
P D15 D16 GND GND
R D17
T D19
D18
D20
VDD
VDD
CSGateEN V DD
1234
QCKE0 QCKE1
Q0 Q1
Q2 DNU
QODT0 QODT1
Q3 Q4
Q5 Q6
NC
QCS0
NC
Q7
Q9
Q11
Q13
Q15
Q17
Q19
NC
QCS1
NC
Q8
Q10
Q12
Q14
Q16
Q18
Q20
56
1186G—04/16/07
2


Part Number ICSSSTUB32871A
Description 27-Bit Registered Buffer
Maker ICS
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