* 28-bit 1:1 registered buffer with parity check functionality
* Supports SSTL_18 JEDEC specification on data inputs and outputs
* Supports LVCMOS switching .

This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been o.

ICSSSTUB32871A

ICSSSTUB32864A

ICSSSTUB32866B

ICSSSTUBF32866A

ICSSSTU32864

ICSSSTU32866

ICSSSTUA32S869B

ICSSSTUAF32865A

ICSSSTUAF32866B

ICSSSTUAF32866C

ICSSSTUAF32868A

ICSSSTUAF32868B

ICSSSTUAF32869A