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ICSSSTUBF32866A - 25-Bit Configurable Registered Buffer

Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

Features

  • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.
  • Supports LVCMOS switching levels on CSR and RESET inputs.
  • Low voltage operation VDD = 1.7V to 1.9V.
  • Available in 96 BGA package.
  • Drop-in replacement for ICSSSTUA32864.
  • Green packages available Pin Configuration 1 A B C D E F G H J K L M N P R T 2 3 4 5 6 Functionality Truth Tabl.

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Datasheet Details

Part number ICSSSTUBF32866A
Manufacturer ICS
File Size 321.61 KB
Description 25-Bit Configurable Registered Buffer
Datasheet download datasheet ICSSSTUBF32866A Datasheet
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www.DataSheet4U.com Integrated Circuit Systems, Inc. ICSSSTUBF32866A Advance Information 25-Bit Configurable Registered Buffer for DDR2 Recommended Application: • DDR2 Memory Modules • Provides complete DDR DIMM solution with ICS97ULP877 • Ideal for DDR2 667, and 800 Product Features: • 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSR and RESET inputs • Low voltage operation VDD = 1.7V to 1.
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