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ICSSSTUBF32866A Datasheet - ICS

25-Bit Configurable Registered Buffer

ICSSSTUBF32866A Features

* 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality

* Supports SSTL_18 JEDEC specification on data inputs and outputs

* Supports LVCMOS switching levels on CSR and RESET inputs

* Low voltage operation VDD = 1.7V to 1.9V

ICSSSTUBF32866A General Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM.

ICSSSTUBF32866A Datasheet (321.61 KB)

Preview of ICSSSTUBF32866A PDF

Datasheet Details

Part number:

ICSSSTUBF32866A

Manufacturer:

ICS

File Size:

321.61 KB

Description:

25-bit configurable registered buffer.
www.DataSheet4U.com Integrated Circuit Systems, Inc. ICSSSTUBF32866A Advance Information 25-Bit Configurable Registered Buffer for DDR2 Recommended.

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ICSSSTUBF32866A 25-Bit Configurable Registered Buffer ICS

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