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9DBL0253 - 2-Output 3.3V LP-HCSL Zero-Delay Buffer

Download the 9DBL0253 datasheet PDF. This datasheet also covers the 9DBL0243 variant, as both devices belong to the same 2-output 3.3v lp-hcsl zero-delay buffer family and are provided as variant models within a single manufacturer datasheet.

Description

The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's Full-Featured PCIe clock family.

4 Common Clock (CC) architectures and also support NVLINK applications.

Features

  • Loss Of Signal (LOS) open drain output.
  • 2 1.
  • 200 MHz Low-Power (LP) HCSL DIF pairs.
  • 9DBL0243 default Zout = 100Ω.
  • 9DBL0253 default Zout = 85Ω.
  • Easy AC-coupling to other logic families; see IDT.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (9DBL0243-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number 9DBL0253
Manufacturer IDT
File Size 350.15 KB
Description 2-Output 3.3V LP-HCSL Zero-Delay Buffer
Datasheet download datasheet 9DBL0253 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
9DBL0252 Zero-Delay/Fanout Buffer Renesas
9DBL0252C 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers Renesas
9DBL0255 2 and 4-Output 3.3V PCIe Gen1-5 Clock Fanout Buffers Renesas
9DBL0242 Zero-Delay/Fanout Buffer Renesas
9DBL0242C 2 to 8-Output 3.3V PCIe Zero-Delay/Fanout Buffers Renesas

Other Datasheets by IDT

Part Number Description
9DBL0252 2-output 3.3V PCIe Zero-Delay Buffer
9DBL0255 PCIe Gen1-5 Clock Fanout Buffers
9DBL02 2-output 3.3V PCIe Zero-Delay Buffer
9DBL0242 2-output 3.3V PCIe Zero-Delay Buffer
9DBL0243 2-Output 3.3V LP-HCSL Zero-Delay Buffer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
2-Output 3.3V LP-HCSL Zero-Delay 9DBL0243 / 9DBL0253 Buffer with LOS Indicator Datasheet Description The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's Full-Featured PCIe clock family. They support PCIe Gen1–4 Common Clock (CC) architectures and also support NVLINK applications. The 9DBL0243 / 9DBL0253 parts have a Loss of Signal (LOS) indicator to support fault-tolerant, high-reliability systems. Typical Applications ▪ PCIe Gen1–4 and NVLINK clock distribution for Riser Cards ▪ Storage and Networking ▪ JBOD ▪ Communications ▪ Access Points Output Features ▪ Loss Of Signal (LOS) open drain output ▪ 2 1–200 MHz Low-Power (LP) HCSL DIF pairs — 9DBL0243 default Zout = 100Ω — 9DBL0253 default Zout = 85Ω ▪ Easy AC-coupling to other logic families; see IDT application note AN-891.
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