2-Output 3.3V LP-HCSL Zero-Delay 9DBL0243 / 9DBL0253
Buffer with LOS Indicator
Datasheet
Description
The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's
Full-Featured PCIe clock family. They support PCIe Gen1–4
Common Clock (CC) architectures and also support NVLINK
applications. The 9DBL0243 / 9DBL0253 parts have a Loss of
Signal (LOS) indicator to support fault-tolerant, high-reliability
systems.
Typical Applications
▪ PCIe Gen1–4 and NVLINK clock distribution for Riser Cards
▪ Storage and Networking
▪ JBOD
▪ Communications
▪ Access Points
Output Features
▪ Loss Of Signal (LOS) open drain output
▪ 2 1–200 MHz Low-Power (LP) HCSL DIF pairs
— 9DBL0243 default Zout = 100Ω
— 9DBL0253 default Zout = 85Ω
▪ Easy AC-coupling to other logic families; see IDT application
note AN-891.
Key Specifications
▪ PCIe Gen1–4 CC compliant in ZDB or fanout buffer mode
▪ Supports NVLINK at 156.25MHz in ZDB or fanout buffer mode
▪ DIF cycle-to-cycle jitter < 50ps
▪ DIF output-to-output skew < 50ps
▪ Bypass Mode additive phase jitter is 0ps typical rms for PCIe
▪ Bypass Mode additive phase jitter 160fs rms typical at 156.25M
(1.5MHz to 10MHz)
Block Diagram
Features
▪ LOS indicator signals loss of input clock; adds fault tolerance,
eases system diagnostics
▪ Direct connection to 100Ω (0243) or 85Ω (0253) transmission
lines; saves 8 resistors compared to standard PCIe devices
▪ 100mW typical power consumption in PLL mode; eliminates
thermal concerns
▪ OE# pin for each DIF output; supports DIF power management
▪ HCSL-compatible differential input; can be driven by common
clock sources
▪ Spread spectrum tolerant; allows reduction of EMI
▪ Outputs blocked until PLL is locked; clean system start-up
▪ Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
▪ 3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
▪ SMBus-selectable features allows optimization to customer
requirements:
— control input polarity
— control input pull-up/downs
— slew rate for each output
— differential output amplitude
— output impedance for each output
▪ Contact IDT for quick-turn customization of SMBus defaults;
allows exact optimization to customer requirements.
▪ 4 × 4 mm 24-VFQFPN; minimal board space
vOE(1:0)#
2
CLK_IN
CLK_IN#
vSADR_tri
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
Spread
Spectrum
Compatible PLL
LOS
Logic
DIF1
DIF1
DIF0
DIF0
LOS
©2017 Integrated Device Technology, Inc.
1
March 15, 2017
