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Integrated Device Technology Electronic Components Datasheet

9DBL0253 Datasheet

2-Output 3.3V LP-HCSL Zero-Delay Buffer

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2-Output 3.3V LP-HCSL Zero-Delay 9DBL0243 / 9DBL0253
Buffer with LOS Indicator
Datasheet
Description
The 9DBL0243 / 9DBL0253 devices are 3.3V members of IDT's
Full-Featured PCIe clock family. They support PCIe Gen1–4
Common Clock (CC) architectures and also support NVLINK
applications. The 9DBL0243 / 9DBL0253 parts have a Loss of
Signal (LOS) indicator to support fault-tolerant, high-reliability
systems.
Typical Applications
PCIe Gen1–4 and NVLINK clock distribution for Riser Cards
Storage and Networking
JBOD
Communications
Access Points
Output Features
Loss Of Signal (LOS) open drain output
2 1–200 MHz Low-Power (LP) HCSL DIF pairs
— 9DBL0243 default Zout = 100
— 9DBL0253 default Zout = 85
Easy AC-coupling to other logic families; see IDT application
note AN-891.
Key Specifications
PCIe Gen1–4 CC compliant in ZDB or fanout buffer mode
Supports NVLINK at 156.25MHz in ZDB or fanout buffer mode
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
Bypass Mode additive phase jitter is 0ps typical rms for PCIe
Bypass Mode additive phase jitter 160fs rms typical at 156.25M
(1.5MHz to 10MHz)
Block Diagram
Features
LOS indicator signals loss of input clock; adds fault tolerance,
eases system diagnostics
Direct connection to 100(0243) or 85(0253) transmission
lines; saves 8 resistors compared to standard PCIe devices
100mW typical power consumption in PLL mode; eliminates
thermal concerns
OE# pin for each DIF output; supports DIF power management
HCSL-compatible differential input; can be driven by common
clock sources
Spread spectrum tolerant; allows reduction of EMI
Outputs blocked until PLL is locked; clean system start-up
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
SMBus-selectable features allows optimization to customer
requirements:
— control input polarity
— control input pull-up/downs
— slew rate for each output
— differential output amplitude
— output impedance for each output
Contact IDT for quick-turn customization of SMBus defaults;
allows exact optimization to customer requirements.
4 × 4 mm 24-VFQFPN; minimal board space
vOE(1:0)#
2
CLK_IN
CLK_IN#
vSADR_tri
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
Spread
Spectrum
Compatible PLL
LOS
Logic
DIF1
DIF1
DIF0
DIF0
LOS
©2017 Integrated Device Technology, Inc.
1
March 15, 2017


Integrated Device Technology Electronic Components Datasheet

9DBL0253 Datasheet

2-Output 3.3V LP-HCSL Zero-Delay Buffer

No Preview Available !

Pin Assignments
Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View
9DBL0243 / 9DBL0253 Datasheet
FB_DNC 1
FB_DNC# 2
VDDR3.3 3
CLK_IN 4
CLK_IN# 5
GNDDIG 6
24 23 22 21 20 19
9DBL0243
9DBL0253
connect EPAD to
GND
7 8 9 10 11 12
18 DIF1#
17 DIF1
16 LOS
15 VDDA3.3
14 NC
13 vOE0#
Pin Descriptions
Table 1. Pin Descriptions
Number
1
Name
FB_DNC
2 FB_DNC#
3 VDDR3.3
4 CLK_IN
5 CLK_IN#
6 GNDDIG
7 SDATA_3.3
8 VDDDIG3.3
9 SCLK_3.3
10 VDDO3.3
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
^v prefix indicates internal 120KOhm pull up AND pull down resistor
(biased to VDD/2)
v prefix indicates internal 120KOhm pull down resistor
Type Description
DNC
DNC
Power
True clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback input
are connected internally on this pin. Do not connect anything to this pin.
Power supply for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately, nominally 3.3V.
Input
Input
Ground
I/O
Power
Input
True input for differential reference clock.
Complementary input for differential reference clock.
Ground pin for digital circuitry.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power).
Clock pin of SMBus circuitry, 3.3V tolerant.
Power Power supply for outputs, nominally 3.3V.
©2017 Integrated Device Technology, Inc.
2
March 15, 2017


Part Number 9DBL0253
Description 2-Output 3.3V LP-HCSL Zero-Delay Buffer
Maker IDT
PDF Download

9DBL0253 Datasheet PDF






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