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ICSSSTUAF32866B - 25-BIT CONFIGURABLE REGISTERED BUFFER

Datasheet Summary

Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation.

All clock and data inputs are compatible with the JEDEC standard for SSTL_18.

The control inputs are LVCMOS.

Features

  • 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality.
  • Supports SSTL_18 JEDEC specification on data inputs and outputs.
  • Supports LVCMOS switching levels on C0, C1, and RESET inputs.
  • Low voltage operation: VDD = 1.7V to 1.9V.
  • Available in 96-ball LFBGA package.

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Datasheet Details

Part number ICSSSTUAF32866B
Manufacturer IDT
File Size 670.97 KB
Description 25-BIT CONFIGURABLE REGISTERED BUFFER
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www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL IDT74SSTUBF32866B Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUBF32866B operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high).
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