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IDT8P34S1204I Datasheet

1:4 LVDS Output 1.8V Fanout Buffer

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1:4 LVDS Output 1.8V Fanout Buffer
IDT8P34S1204I
DATA SHEET
General Description
The IDT8P34S1204I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1204I is characterized to operate from a 1.8V power
supply. Guaranteed low output-to-output and part-to-part skew
characteristics make the IDT8P34S1204I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
Four low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
Maximum input clock frequency: 1.2GHz
LVCMOS/LVTTL interface levels for the control input select
Output skew: 10ps (typical)
Propagation delay: 400ps (maximum)
Low additive phase jitter, RMS; fREF = 156.25MHz,
10kHz - 20MHz: 43fs (typical)
Device current consumption (IDD): 78mA (maximum)
Full 1.8V supply voltage
lead-free (RoHS 6), 16-Lead VFQFN package
-40°C to 85°C ambient operating temperature
Block Diagram
VDD
CLK0
nCLK0
Pulldown
Pullup/Pulldown
VDD
CLK1
nCLK1
Pulldown
Pullup/Pulldown
0 fREF
1
SEL Pulldown
VREF
Voltage
Reference
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
12 11 10 9
Q2 13
nQ2 14
Q3 15
nQ3 16
1234
8 VREF
7 nCLK0
6 CLK0
5 VDD
IDT8P34S1204I
16-Lead VFQFN
3mm x 3mm x 0.925mm package body
1.7mm x 1.7mm ePad Size
NL Package
Top View
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
1
©2014 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

IDT8P34S1204I Datasheet

1:4 LVDS Output 1.8V Fanout Buffer

No Preview Available !

IDT8P34S1204I Data Sheet
1:4 LVDS Output 1.8V Fanout Buffer
Pin Description and Pin Characteristic Tables
Table 1. Pin DescriptionsNote1.
Number
Name
Type
1
GND
Power
Description
Power supply ground.
2
SEL
Input
Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
3
CLK1
Input
Pulldown Non-inverting differential clock/data input.
4
nCLK1
Input
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
5 VDD Power
Power supply pin.
6
CLK0
Input
Pulldown Non-inverting differential clock/data input.
7
nCLK0
Input
Pullup/
Pulldown
Inverting differential clock/data input. VDD/2 default when left floating.
8
VREF
Output
Bias voltage reference. Provides an input bias voltage for the
CLK[0:1], nCLK[0:1] input pairs in AC-coupled applications. Refer to
Figures 2B and 2C for applicable AC-coupled input interfaces.
9, 10
Q0, nQ0
Output
Differential output pair 0. LVDS interface levels.
11, 12
Q1, nQ1
Output
Differential output pair 1. LVDS interface levels.
13, 14
Q2, nQ2
Output
Differential output pair 2. LVDS interface levels.
15, 16
Q3, nQ3
Output
Differential output pair 3. LVDS interface levels.
1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLDOWN Input Pulldown Resistor
RPULLUP
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3. SEL Input Function TableNote1.
Input
SEL
0 (default)
Operation
CLK0, nCLK0 is the selected differential clock input.
1 CLK1, nCLK1 is the selected differential clock input.
1. SEL is an asynchronous control.
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014
2
©2014 Integrated Device Technology, Inc.


Part Number IDT8P34S1204I
Description 1:4 LVDS Output 1.8V Fanout Buffer
Maker IDT
Total Page 19 Pages
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