900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




Integrated Silicon Solution Electronic Components Datasheet

IS42S32200 Datasheet

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

No Preview Available !

IS42S32200
512K Bits x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
ISSI®
PRELIMINARY INFORMATION
August 2003
FEATURES
• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Internal bank for hiding row access/precharge
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
– (1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Self refresh modes
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Industrial temperature availability
• Package 400-mil 86-pin TSOP II
PIN DESCRIPTIONS
A0-A10
Address Input
BA0, BA1
Bank Select Address
I/O0 to I/O31 Data I/O
CLK System Clock Input
CKE
CS
Clock Enable
Chip Select
RAS
Row Address Strobe Command
CAS
WE
Column Address Strobe Command
Write Enable
DQM0 to DQM3 Input/Output Mask
OVERVIEW
ISSI's 64Mb Synchronous DRAM IS42S32200 is organized
as 524,288 bits x 32-bit x 4-bank for improved performance.
The synchronous DRAMs achieve high-speed data transfer
using pipeline architecture. All inputs and outputs signals
refer to the rising edge of the clock input.
PIN CONFIGURATION
(86-Pin TSOP (Type II)
VCC
I/O0
VCCQ
I/O1
I/O2
GNDQ
I/O3
I/O4
VCCQ
I/O5
I/O6
GNDQ
I/O7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
DQM2
VCC
NC
I/O16
GNDQ
I/O17
I/O18
VCCQ
I/O19
I/O20
GNDQ
I/O21
I/O22
VCCQ
I/O23
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86 GND
85 I/O15
84 GNDQ
83 I/O14
82 I/O13
81 VCCQ
80 I/O12
79 I/O11
78 GNDQ
77 I/O10
76 I/O9
75 VCCQ
74 I/O8
73 NC
72 GND
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 GND
57 NC
56 I/O31
55 VCCQ
54 I/O30
53 I/O29
52 GNDQ
51 I/O28
50 I/O27
49 VCCQ
48 I/O26
47 I/O25
46 GNDQ
45 I/O24
44 GND
Vcc
GND
VccQ
GNDQ
NC
Power
Ground
Power Supply for I/O Pin
Ground for I/O Pin
No Connection
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00B
08/14/03
1


Integrated Silicon Solution Electronic Components Datasheet

IS42S32200 Datasheet

512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

No Preview Available !

IS42S32200
ISSI ®
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 2,048
rows by 256 columns by 32 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE
function enabled. Precharge one bank while accessing one
of the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.
SDRAM read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0, BA1
select the bank; A0-A10 select the row). The READ or
WRITE commands in conjunction with address bits reg-
istered are used to select the starting column location for
the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
COMMAND
DECODER
&
CLOCK
GENERATOR
MODE
REGISTER
10
ROW
ADDRESS
10 LATCH
COLUMN
ADDRESS LATCH
BURST COUNTER
COLUMN
ADDRESS BUFFER
REFRESH
CONTROLLER
SELF
REFRESH
CONTROLLER
REFRESH
COUNTER
ROW
ADDRESS
BUFFER
10
DATA IN
BUFFER
32 32
DQM0-3
I/O 0-31
DATA OUT
BUFFER
32 32
Vcc/VccQ
GND/GNDQ
2048
2048
2048
MEMORY CELL
10
2048
ARRAY
BANK 0
SENSE AMP I/O GATE
BANK CONTROL LOGIC
256
(x 32)
COLUMN DECODER
2 Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION Rev. 00B
08/14/03


Part Number IS42S32200
Description 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
Maker ISSI
Total Page 30 Pages
PDF Download

IS42S32200 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 IS42S32200 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
ISSI
2 IS42S32200E SYNCHRONOUS DYNAMIC RAM
ISSI





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy