IS42SM16400G Datasheet | ISSI

1M x 16Bits x 4Banks Low Power Synchronous DRAM Description These IS42SM16400G are Low Power 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 1,048,576 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are patible with LVCMOS. Features - JEDEC standard 3.3V power supply. - Auto refresh and self refresh. - All pins are patible with LVCMOS interface. - 4K refresh cycle y / 64ms. - Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst. - Programmable CAS Latency : 2,3 clocks. - Programmable Driver Strength Control - Full Strength or 1/2, 1/4 of Full Strength - Deep Power Down Mode Mode. - All inputs and outputs referenced to the positive edge of the system clock. - Data mask function by DQM. - Internal 4 banks operation operation. - Burst Read Single Write operation. - Special Function Support. - PASR(Partial Array Self Refresh) - Auto TCSR(Temperature pensated Self Refresh) - Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge. Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon S S Solution, Inc. does not remend the use of f any of f its products in life f support applications where the failure f or malfunction of the product can reasonably be...