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IS61QDB251236C - 18Mb QUAD Synchronous SRAM

Download the IS61QDB251236C datasheet PDF. This datasheet also covers the IS61QDB21M18C variant, as both devices belong to the same 18mb quad synchronous sram family and are provided as variant models within a single manufacturer datasheet.

Description

The 18Mb IS61QDB251236C and IS61QDB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.

Features

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising ed.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61QDB21M18C-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution
IS61C256 32K x 8 Low Voltage CMOS STATIC RAM Integrated Silicon Solution
IS61C25616 256K x 8 High Speed CMOS STATIC RAM Integrated Silicon Solution
IS61C25616AL 256K x 16 HIGH-SPEED CMOS STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61QDB251236A 18Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M18A 18Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M18C 18Mb QUAD Synchronous SRAM
IS61QDB21M36 QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36A 36Mb QUAD (Burst 2) Synchronous SRAM

Full PDF Text Transcription

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IS61QDB21M18C IS61QDB251236C 1Mx18, 512Kx36 18Mb QUAD (Burst 2) Synchronous SRAM JANUARY 2021 FEATURES  512Kx36 and 1Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with EARLY write operation.  Double Data Rate (DDR) interface for read and write input ports.  Fixed 2-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two output clocks (C and C#) for data output control.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
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