IS61QDB251236A - 18Mb QUAD (Burst 2) Synchronous SRAM

Product Overview

ISSI

Datasheet Details

Part number	IS61QDB251236A
Manufacturer	ISSI
File Size	588.46 KB
Description	18Mb QUAD (Burst 2) Synchronous SRAM
Datasheet	IS61QDB251236A Datasheet
Note	This datasheet PDF includes multiple part numbers: IS61QDB251236A, IS61QDB21M18A. Please refer to the document for exact specifications by model.
Additional preview pages of the IS61QDB251236A datasheet.

Product details

Description

The and are synchronous, high-performance CMOS static random access memory (SRAM) devices.These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.Refer to the for a description of the basic operations of these SRAMs.The input address bus operates at double data rate.The following are registered internally on the rising edge of the K clock: Read

Features

512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising ed.

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Other Datasheets by ISSI

IS61QDB251236C - 18Mb QUAD Synchronous SRAM
IS61QDB21M18A - 18Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M18C - 18Mb QUAD Synchronous SRAM
IS61QDB21M36 - QUAD (Burst of 2) Synchronous SRAMs
IS61QDB21M36A - 36Mb QUAD (Burst 2) Synchronous SRAM
IS61QDB21M36C - 36Mb QUAD Synchronous SRAM

Published: Jun 10, 2016 |