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* Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one cloc.
The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the r.
The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the r.
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