IDT8P34S1208I - 1:8 LVDS Output 1.8V Fanout Buffer

The IDT8P34S1208I is a high-performance differential LVDS fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The IDT8P34S1208I is characterized to operate from a 1.8V power supply.

• Eight low skew, low additive jitter LVDS output pairs Two selectable, differential clock input pairs Differential CLK, nCLK pairs can accept the following differential input levels: LVDS, CML Maximum input clock frequency: 1.2GHz (maximum) LVCMOS/LVTTL interface levels for the control input select pin Output skew: 20ps (typical) Propagation delay: 315ps (typical) Low additive phase jitte.