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IDT8P34S1208I Datasheet

1:8 LVDS Output 1.8V Fanout Buffer

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1:8 LVDS Output 1.8V Fanout Buffer
IDT8P34S1208I
DATA SHEET
General Description
The IDT8P34S1208I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1208I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1208I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and eight low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
Eight low skew, low additive jitter LVDS output pairs
Two selectable, differential clock input pairs
Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
Maximum input clock frequency: 1.2GHz (maximum)
LVCMOS/LVTTL interface levels for the control input select pin
Output skew: 20ps (typical)
Propagation delay: 315ps (typical)
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,
12kHz - 20MHz: 41fs (typical)
Full 1.8V supply voltage
Lead-free (RoHS 6), 28-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram.
VREF0
CLK0
nCLK0
Voltage
Reference
VDD
CLK1
nCLK1
VDD
fREF
SEL
VREF1
Voltage
Reference
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pin Assignment
21 20 19 18 17 16 15
Q4 22
IDT8P34S1208I
14 GND
nQ4 23
28-lead VFQFN
13 nQ0
Q5 24 5.0mm x 5.0mm x 0.75mm 12 Q0
package body
nQ5 25
11 VREF0
Q6 26 3.25mm x 3.25mm ePad Size 10 nCLK0
nQ6 27
NB Package
9 CLK0
VDD 28
Top View
8 VDD
1234567
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
1
©2014 Integrated Device Technology, Inc.


Integrated Device Technology Electronic Components Datasheet

IDT8P34S1208I Datasheet

1:8 LVDS Output 1.8V Fanout Buffer

No Preview Available !

IDT8P34S1208I Data Sheet
1:8 LVDS OUTPUT 1.8V FANOUT BUFFER
Pin Description and Pin Characteristic Tables
Table 1. Pin DescriptionsNote 1.
Number
Name
Type
Description
1, 14
GND
Power
Power supply pin.
2, 3
Q7, nQ7
Output
Differential output pair 7. LVDS interface levels.
4
SEL
Input
Pulldown Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
5
CLK1
Input
Pulldown Non-inverting differential clock/data input 1.
6
nCLK1
Input
Pullup/
Pulldown Inverting differential clock/data input 1. VDD/2 default when left floating.
7
VREF1
Output
Bias voltage reference. Provides an input bias voltage for the CLK1, nCLK1
input pair in AC-coupled applications. Refer to Figures 2B and 2C for
applicable AC-coupled input interfaces.
8, 15, 28
9
10
11
VDD
CLK0
nCLK0
VREF0
Power
Input
Input
Output
Pulldown
Pullup/
Pulldown
Power supply pin.
Non-inverting differential clock/data input 0.
Inverting differential clock/data input 0. VDD/2 default when left floating.
Bias voltage reference. Provides an input bias voltage for the CLK0, nCLK0
input pair in AC-coupled applications. Refer to Figures 2B and 2C for
applicable AC-coupled input interfaces.
12, 13
Q0, nQ0
Output
Differential output pair 0. LVDS interface levels.
16, 17
Q1, nQ1
Output
Differential output pair 1. LVDS interface levels.
18, 19
Q2, nQ2
Output
Differential output pair 2. LVDS interface levels.
20, 21
Q3, nQ3
Output
Differential output pair 3. LVDS interface levels.
22, 23
Q4, nQ4
Output
Differential output pair 4. LVDS interface levels.
24, 25
Q5, nQ5
Output
Differential output pair 5. LVDS interface levels.
26, 27
Q6, nQ6
Output
Differential output pair 6. LVDS interface levels.
1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
Table 3. SEL Input Function TableNote 1.
Input
SEL Operation
0 CLK0, nCLK0 is the selected differential clock input.
1 CLK1, nCLK1 is the selected differential clock input.
1. SEL is an asynchronous control.
IDT8P34S1208NBGI REVISION A JANUARY 22, 2014
2
©2014 Integrated Device Technology, Inc.


Part Number IDT8P34S1208I
Description 1:8 LVDS Output 1.8V Fanout Buffer
Maker Integrated Device
Total Page 18 Pages
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