IDT71V2546, IDT71V2548, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
Advance / Load
N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled
Read / Write
I N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the
low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of
I LOW Synchronous byte write enables. Each 9-bit b yte has its own active low byte write enable. On load write cycles
(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
sampled high. The appro priate byte(s) of data are written into the de vice two cycles later. BW1-BW4 can all be
tied low if always doing write to the entire 36-bit word.
I LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V2546/48. (CE1 or
CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
The ZBTTM has a two cycle de select, i.e., the data bus will tri-state two clo ck cycles after deselect is initiated.
I HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has inverted
polarity but otherwise identical to CE1 and CE2.
I N/A This is the clock input to the IDT71V2546/48. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
Linear Burst Order
LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
I LOW Asynchronous output enable. OE must be low to read data from the 71V2546/48. When OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
Test Mode Select
N/A Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Test Data Input
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured o n rising edge of TCK,
while test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
Test Data Output
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the
Optional Asynchronous JTAG reset. Can be used to reset the TAP co ntroller, but not required. JTAG reset
I LOW occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup.
Synchronous sleep mode inp ut. ZZ HIGH will gate the CLK internally and power down the IDT71V2546/2548 to
I HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
N/A N/A 3.3V core power supply.
N/A N/A 2.5V I/O Supply.
N/A N/A Ground.
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
5294 tbl 02