IDT71V546 outputs equivalent, 128k x 36/ 3.3v synchronous sram with zbt feature/ burst counter and pipelined outputs.
128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between wr.
4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip en.
The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given.
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