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QS5919T - LOW SKEW TTL PLL CLOCK DRIVER

General Description

The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs.

Eight outputs are available: 2xQ, Q 0-Q4, Q5, Q/2.

Careful layout and design ensure < 350ps skew between the Q0-Q4, and Q/2 outputs.

Key Features

  • 5V operation Low noise TTL level outputs < 350ps output skew, Q0.
  • Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequ.

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Datasheet Details

Part number QS5919T
Manufacturer Integrated Device Technology
File Size 163.47 KB
Description LOW SKEW TTL PLL CLOCK DRIVER
Datasheet download datasheet QS5919T Datasheet

Full PDF Text Transcription for QS5919T (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for QS5919T. For precise diagrams, and layout, please refer to the original PDF.

www.DataSheet.co.kr QS5919T LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INDUSTRIAL TEMPERATURE RANGE LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILT...

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PERATURE RANGE LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • • • • • • • • • • • • 5V operation Low noise TTL level outputs < 350ps output skew, Q0–Q4 2xQ output, Q outputs, Q output, Q/2 output Outputs 3-state and reset while OE/RST low PLL disable feature for low frequency testing Internal loop filter RC network Functional equivalent to Motorola MC88915 Positive or negative edge synchronization (PE) Balanced drive outputs ±24mA 160MHz maximum frequency (2xQ output) Available in QSOP and PLCC packages QS5919T DESCRIPTION The QS5919T Clock Driver uses an internal phase locked loop (PLL) to lock low

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