Integrated Device Technology QS5930T
The QS5930T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to a reference clock input. The QS5930T includes an internal RC filter which provides excellent jitter characteristics and eliminates the need for external components. The QS5930T is designed for use in cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, and mainframe systems.| Part No. | QS5930T |
|---|---|
| Datasheet | QS5930T Download |
| Manufacturer |  Integrated Device Technology |
| Description | LOW SKEW CMOS PLL CLOCK DRIVER |
| Buy | Stock & Price |
FEATURES
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● 5V operation Q/2 output, 5 Q outputs Useful for Pentium, PowerPC, and PCI systems Internal loop filter RC network Low noise TTL level outputs <250ps rising edge output skew Balanced drive outputs ±24mA PLL bypass feature for low frequency testing Internal VCO/2 option for wider frequency range Outputs tri-state and reset while OE/RST is low ESD > 2000V Latch up > -300mA Available in QSOP package QS5930T
DESCRIPTION
Six outputs are available: Q0–Q4, Q/2. Careful layout and design ensure < 250ps skew between the Q0–Q4, and Q/2 outputs. Various combinations of feedback and a divide-by-2 in the VCO path allow applications to be customized for linear VCO operation over a wide range of input SYNC frequencies. The PLL can also be disabled by the PLL_EN signal to allow low frequency or DC testing. Several can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. In the QSOP package, the QS5930T clock driver represents the best value in small form factor, high-performance clock management products.
