DESCRIPTION s Max. shift frequency of 700MHz s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE.

s Max. shift frequency of 700MHz s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE min. of
  –170mA s Industry standard 100K ECL levels s Internal 75KΩ input pul.

SY100S336

SY100S331

SY100S301

SY100S302

SY100S304

SY100S307

SY100S313

SY100S314

SY100S317

SY100S318

SY100S321

SY100S322

SY100S324