SY100S336 Datasheet | Micrel Semiconductor

Micrel, Inc. 4-STAGE COUNTER/ SHIFT REGISTER Features DESCRIPTION s Max. shift frequency of 700MHz s Clock to Q delay max. of 1100ps s IEE min. of - 170m A s Internal 75KΩ input pull-down resistors s Industry standard 100K ECL levels s Extended supply voltage option: VEE = - 4.2V to - 5.5V s Voltage and temperature pensation for improved noise immunity s 50% faster than Fairchild 300K at lower power s Function and pinout patible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S336 functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls (CEP, CET) are provided. The CET input also functions as the Serial Data input (S0) for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation. When the device is in the counting mode, the Terminal Count (TC) goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the Q3 output. The flexiblity provided by the TC/Q3 output and the D0/ CET input allows these signals to be interconnected from one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets (Pn) allow initialization of the counter by entering data in parallel to preset the counter. A logic HIGH on the Master Reset (MR) overrides all other inputs and asynchronously clears the flip-flops. An additional synchronous Clear is provided, as well as a plement function which synchronously inverts the contents of the flip-flops. All inputs have 75KΩ pulldown resistors. PIN NAMES Pin CP CEP D0/CET S0 - S2 MR VEES VCCA P0 - P3 D3 TC Q0 -...