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Micrel, Inc.
NOT RECOMMENDED FOR NEW DESIGNS
TRIPLE D FLIP-FLOP
SY100S331
SY100S331
FEATURES
DESCRIPTION
■ Max. toggle frequency of 800MHz ■ Differential outputs ■ IEE min. of –80mA ■ Industry standard 100K ECL levels ■ Extended supply voltage option:
VEE = –4.2V to –5.5V ■ Voltage and temperature compensation for improved
noise immunity ■ Internal 75kΩ input pull-down resistors ■ 150% faster than Fairchild ■ 40% lower power than Fairchild ■ Function and pinout compatible with Fairchild F100K ■ Available in 28-pin PLCC package
The SY100S331 offers three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is controlled by a common clock (CPc), as well as its own clock pulse (CPn).
SY100S331 Datasheet
