SY100S336A Datasheet | Micrel Semiconductor

Micrel, Inc. ENHANCED 4-STAGE COUNTER/SHIFT REGISTER Features DESCRIPTION s Max. shift frequency of 700MHz s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE min. of - 170m A s Industry standard 100K ECL levels s Internal 75KΩ input pull-down resistors s Extended supply voltage option: VEE = - 4.2V to - 5.5V s Voltage and temperature pensation for improved noise immunity s 50% faster than Fairchild 300K at lower power s Function and pinout patible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages PIN NAMES Pin CP CEP D0/CET S0 - S2 MR VEES VCCA P0 - P3 D3 TC Q0 - Q3 Q0 - Q3 Function Clock Pulse Input Count Enable Parallel Input (Active LOW) Serial Data Input/Count Enable Trickle Input (Active LOW) Select Inputs Master Reset Input VEE Substrate VCCO for ECL Outputs Preset Inputs Serial Data Input Terminal Count Output Data Outputs plementary Data Outputs The SY100S336A is functionally the same as the SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. The SY100S336A functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs (Sn) are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls (CEP, CET) are provided. The CET input also functions as the Serial Data input (S0) for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation. When the device is in the counting mode, the Terminal Count (TC) goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the...