SY100S336A Description
shift frequency of 700MHz s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE min. of 170mA s Industry standard 100K ECL levels s Internal 75KΩ input pull-down resistors s Extended supply voltage option:.
SY100S336A Key Features
- S2 MR VEES VCCA P0
- P3 D3 TC Q0