- Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differenti.

M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is regi.

M2V12D30TP-75L

M2V12D30TP-10

M2V12D30TP-10L

M2V12D30TP

M2V12D20TP

M2V12D20TP-10

M2V12D20TP-10L

M2V12D20TP-75

M2V12D20TP-75L

M2V28D20ATP-10

M2V28D20ATP-75

M2V28D30ATP-10

M2V28D30ATP-75