V58C265804S Datasheet | Mosel Vitelic Corp

Features s 4 banks x 2Mbit x 8 organization s High speed data transfer rates with system frequency up to 166 MHz s Data Mask for Write Control (DM) s Four Banks controlled by BA0 & BA1 s Programmable CAS Latency: 2, 2.5, 3 s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type s Automatic and Controlled Precharge mand s Suspend Mode and Power Down Mode s Auto Refresh and Self Refresh s Refresh Interval: 4096 cycles/64 ms s Available in 66-pin 400 mil TSOP-II s SSTL-2 patible I/Os s Double Data Rate (DDR) s Bidirectional Data Strobe (DQs) for input and output data, active on both edges s On-Chip DLL aligns DQ and DQs transitions with CLK transitions s Differential clock inputs CLK and CLK s Power Supply 2.5V ± 0.2V Description The V58C265804S is a four bank DDR DRAM organized as 4 banks x 2Mbit x 8. The V58C265804S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS. Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Device Usage Chart Operating Temperature Range 0°C to 70 °C Package Outline JEDEC 66 TSOP II - CLK Cycle Time (ns) - 6 - Power Std. - -7 - -8 - L - Temperature Mark Blank V58C265804S Rev. 1.3 January 2000 MOSEL VITELIC 66 Pin Plastic TSOP-II PIN CONFIGURATION Top View VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33...