MC100ES6254 Datasheet | Motorola Semiconductor

Features : - Fully differential architecture from input to all outputs - Si Ge technology supports near-zero output skew - - - - Supports DC to 3GHz operation1 of clock or data signals LVPECL patible differential clock inputs and outputs LVCMOS patible control inputs Single 3.3 V or 2.5 V supply Freescale Semiconductor, Inc... 2.5/3.3 V DIFFERENTIAL LVPECL 2x2 CLOCK SWITCH AND FANOUT BUFFER - 50 ps maximum device skew1 - Synchronous output enable eliminating output runt pulse generation and metastability - Standard 32 lead LQFP package - Industrial temperature range FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A Functional Description MC100ES6254 is designed for very skew critical differential clock distribution systems and supports clock frequencies from DC up to 3.0 GHz. Typical applications for the MC100ES6254 are primary clock distribution, switching and loopback systems of high-performance puter, networking and telemunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 speed munication systems. Primary purpose of the MC100ES6254 is high-speed clock switching applications. In addition, the MC100ES6254 can be configured as single 1:6 or dual 1:3 LVPECL fanout buffer for clock signals, or as loopback device in highspeed data applications. The MC100ES6254 can be operated from a 3.3 V or 2.5 V positive supply without the requirement of a negative supply line. The device is functional up to 3 GHz and characterized up to 2.7 GHz. REV 3 © Motorola, Inc. 2004 For More Information On This Product, Go to: .freescale. Freescale Semiconductor, Inc. MC100ES6254/D VCC Bank A CLK0 CLK0 0 1 QA0 QA0 QA1 QA1 QA2 QA2 VCC CLK1 CLK1 Bank B 0 1 Freescale Semiconductor, Inc... SEL0 SEL1 QB0 QB0 QB1 QB1 QB2 QB2 OEA OEB Sync Figure 1. MC100ES6254 Logic Diagram CLK0 CLK0 SEL0 GND 18 17 16 15 14 13 QB2 QB2 VCC QB1 QB1 VCC QB0 QB0 QA2 QA2 VCC QA1 QA1 VCC QA0...