Overview: SS77LL33223366UU22MM SS77LL33221188UU22MM 11MMxx3366 && 22MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM ww// OODDTT 36Mb DDRII+ CIO BL2 w/ ODT SRAM Specification
(2.5 Clock Read Latency)
165FBGA with Pb & Pb Free
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Rev. 1.3 Mar. 2014 -1- S7L3236U2M S7L3218U2M 1Mx36 & 2Mx18 DDRII+ CIO BL2 SRAM w/ ODT Document Title
1Mx36 & 2Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM w/ ODT (2.5 Clock Read Latency) Revision History Rev. No. History 0.0 Initial Draft 1.0 Final spec release Add DC current spec value 1.1 Add 400MHz speed binning 1.2 Change Thermal Resistance θJA value from 20.8°C/W to 16.3°C/W 1.3 Updated Application Information Updated Timing Wave Forms (Corrected typos) Draft Date
Sep. 2012 Feb. 2013 Remark
Preliminary Final Mar. 2013 Apr. 2013 Final Final Mar. 2014 Final Rev. 1.3 Mar. 2014 -2- S7L3236U2M S7L3218U2M 1Mx36 & 2Mx18 DDRII+ CIO BL2 SRAM w/ ODT 1Mx36 & 2Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM w/ ODT (2.
