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SSTU32865 Datasheet 28-bit 1:2 registered buffer

Manufacturer: NXP Semiconductors

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General Description

The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules.

It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs.

The SSTU32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active-LOW).

Overview

www.DataSheet4U.com SSTU32865 1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM applications Rev.

02 — 28 September 2004 Product data sheet 1.

Key Features

  • s 28-bit data register supporting DDR2 s Fully compliant to JEDEC standard JESD82-9 s Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (i. e. 2 × SSTU32864 or 2 × SSTU32866) s Parity checking function across 22 input data bits s Parity out signal s Controlled output impedance drivers enable optimal signal integrity and speed s Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation delay, 2.0 ns max. mass-switc.

More Datasheets from NXP Semiconductors

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SSTUB32868 1.8 V 28-bit 1 : 2 configurable registered buffer with parity
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SSTUH32865 1.8V 28-bit high output drive 1:2 registered buffer
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