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SSTUA32866 Datasheet

configurable registered buffer

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SSTUA32866
1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
with parity for DDR2-667 RDIMM applications
Rev. 01 — 15 July 2005
Product data sheet
1. General description
The SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2
memory modules requiring a parity checking function. It is defined in accordance with the
JEDEC standard for the SSTUA32866 registered buffer. The register is configurable
(using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in
the latter configuration can be designated as Register A or Register B on the DIMM.
The SSTUA32866 accepts a parity bit from the memory controller on its parity bit
(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs
and indicates whether a parity error has occurred on its open-drain QERR pin
(active LOW). The convention is even parity, that is, valid parity is defined as an even
number of ones across the DIMM-independent data inputs combined with the parity input
bit.
The SSTUA32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package
(13.5 mm × 5.5 mm).
2. Features
s Configurable register supporting DDR2 up to 667 MT/s Registered DIMM applications
s Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode
s Controlled output impedance drivers enable optimal signal integrity and speed
s Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching propagation
delay; 2.0 ns max. mass-switching)
s Supports up to 450 MHz clock frequency of operation
s Optimized pinout for high-density DDR2 module design
s Chip-selects minimize power consumption by gating data outputs from changing state
s Supports SSTL_18 data inputs
s Checks parity on the DIMM-independent data inputs
s Partial parity output and input allows cascading of two SSTUA32866s for correct parity
error processing
s Differential clock (CK and CK) inputs
s Supports LVCMOS switching levels on the control and RESET inputs
s Single 1.8 V supply operation (1.7 V to 2.0 V)
s Available in 96-ball, 13.5 × 5.5 mm, 0.8 mm ball pitch LFBGA package
3. Applications
s 400 MT/s to 667 MT/s DDR2 registered DIMMs desiring parity checking functionality


NXP Semiconductors Electronic Components Datasheet

SSTUA32866 Datasheet

configurable registered buffer

No Preview Available !

SSTUA32866 pdf
Philips Semiconductors
SSTUA32866
1.8 V DDR2-667 configurable registered buffer with parity
4. Ordering information
Table 1: Ordering information
Tamb = 0 °C to +70 °C.
Type number
Solder process
Package
Name
Description
Version
SSTUA32866EC/G Pb-free (SnAgCu solder LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
ball compound)
96 balls; body 13.5 × 5.5 × 1.05 mm
SSTUA32866EC
SnPb solder ball
compound
LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1
96 balls; body 13.5 × 5.5 × 1.05 mm
5. Functional diagram
RESET
CK
CK
VREF
DCKE
DODT
DCS
CSR
SSTUA32866
1D
C1
R
1D
C1
R
1D
C1
R
QCKEA
QCKEB (1)
QODTA
QODTB (1)
QCSA
QCSB (1)
D2 0
1
1D
C1
R
Q2A
Q2B (1)
to 10 other channels
(D3, D5, D6, D8 to D14)
002aab388
(1) Disabled in 1 : 1 configuration.
Fig 1. Functional diagram of SSTUA32866; 1 : 2 Register A configuration with C0 = 0 and
C1 = 1 (positive logic)
9397 750 14759
Product data sheet
Rev. 01 — 15 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2 of 27


Part Number SSTUA32866
Description configurable registered buffer
Maker NXP
Total Page 27 Pages
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