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DS32EL0124 - Deserializer

Datasheet Summary

Description

The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber.

Features

  • 5-bit LVDS parallel data interface Programmable Receive Equalization Selectable DC-balance decoder Selectable De-scrambler Remote Sense for automatic detection and negotiation of link status No external receiver reference clock required LVDS parallel interface Programmable LVDS output clock delay Supports output data-valid signaling Supports keep-alive clock output On chip LC VCOs Redundant seri.

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DS32EL0124/DS32ELX0124 125 — 312.5 MHz Deserializer with DDR LVDS Parallel Interface PRELIMINARY May 9, 2008 DS32EL0124 DS32ELX0124 125 MHz — 312.5 MHz Deserializer with DDR LVDS Parallel Interface General Description The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly www.DataSheet4U.com interface. The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
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