Datasheet4U Logo Datasheet4U.com

DS90CR282 - 28-Bit Channel Link

Download the DS90CR282 datasheet PDF. This datasheet also covers the DS90CR281 variant, as both devices belong to the same 28-bit channel link family and are provided as variant models within a single manufacturer datasheet.

Description

The DS90CR281 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS90CR281_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DS90CR285 +3.3V Rising Edge Data Strobe LVDS Texas Instruments
DS90CR286 +3.3V Rising Edge Data Strobe LVDS Texas Instruments
DS90CR286A 3.3-V Rising Edge Data Strobe LVDS Receiver Texas Instruments
DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver Texas Instruments
DS90CR287 +3.3V Rising Edge Data Strobe LVDS Texas Instruments

Other Datasheets by National Semiconductor (Texas Instruments)

Part Number Description
DS90CR281 28-Bit Channel Link
DS90CR283 28-Bit Channel Link
DS90CR284 28-Bit Channel Link
DS90CR285 +3.3V Rising Edge Data Strobe LVDS
DS90CR286 +3.3V Rising Edge Data Strobe LVDS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90CR281/DS90CR282 28-Bit Channel Link July 1997 DS90CR281/DS90CR282 28-Bit Channel Link General Description The DS90CR281 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR282 receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 28 bits of TTL data are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 1.12 Gbit/s (140 Mbytes/s). The multiplexing of the data lines provides a substantial cable reduction.
Published: |