NB3N111K Description
The NB3N111K is a differential 1:10 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N111K is designed with PCI Express HCSL clock distribution and FBDIMM applications in mind. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals per Figures 7, 8,.
NB3N111K Key Features
- Typical Input Clock Frequency 100, 133, 166, or 400 MHz
- 220 ps Typical Rise and Fall Times
- 800 ps Typical Propagation Delay
- Dtpd 100 ps Maximum Propagation Delay Variation per Diff Pair
- 0.1 ps Typical RMS Additive Phase Jitter
- LVDS Output Levels Optional with Interface Termination
- Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V
- Typical HCSL Output Levels (700 mV Peak-to-Peak)
- LVDS Output Levels with Interface Termination
- These are Pb-Free Devices