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NB3N1900K Datasheet

3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer

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NB3N1900K pdf
NB3N1900K
3.3V 100/133 MHz
Differential 1:19 HCSL
Clock ZDB/Fanout Buffer for
PCIe[
Description
The NB3N1900K differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is
optimized to support 100 MHz and 133 MHz frequency operation.
The NB3N1900K supports HCSL output levels.
Features
Fixed Feedback Path for Lowest Input−to−Output Delay
Eight Dedicated OE# Pins for Hardware Control of Outputs
PLL Bypass Configurable for PLL or Fanout Operation
Selectable PLL Bandwidth
Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
SMBus Programmable Configurations
100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
Cycle−to−Cycle Jitter: < 50 ps
Output−to−Output Skew: < 65 ps
Input−to−Output Delay: Fixed at 0 ps
Input−to−Output Delay Variation: < 50 ps
Phase Jitter: PCIe Gen3 < 1 ps rms
Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
QFN 72−pin Package, 10 mm x 10 mm
These are Pb−Free Devices
www.onsemi.com
MARKING
DIAGRAM*
1 72
QFN72
MN SUFFIX
CASE 485DK
1
NB3N
1900K
AWLYYWWG
NB3N1900K = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 20 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 4
1
Publication Order Number:
NB3N1900K/D


  ON Semiconductor Electronic Components Datasheet  

NB3N1900K Datasheet

3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer

No Preview Available !

NB3N1900K pdf
OE[5:12]#
8
NB3N1900K
CLK_IN
CLK_IN#
SSC Compatible
PLL
MUX
100M_133M#
HBW_BYP_LBW#
SA_0
SA_1
PWRGD/PWRDN#
SDA
SCL
Control
Logic
NOTE: Even though the feedback is fixed FB_OUT and FB_OUT# still needs a
termination network for the part to function.
IREF
Figure 1. Simplified Block Diagram of NB3N1900K
FB_OUT
FB_OUT#
DIF[18:0]
DIF[18:0]#
www.onsemi.com
2


Part Number NB3N1900K
Description 3.3V 100/133MHz Differential 1:19 HCSL Clock ZDB/Fanout Buffer
Maker ON Semiconductor
Total Page 21 Pages
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