NBSG53A divider equivalent, 2.5v/3.3v sige selectable differential clock and data d flip-flop/clock divider.
* Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 3, 5, 7, 9, and 10)
* Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 4, 6,.
Pin Name
I/O
Description
1 VTCLK
− Internal 50 W Termination Pin. See Table 4.
2
CLK
ECL, CML,
Inverted Differential Input.
LVCMOS, LVDS,
LVTTL Input
3
CLK
ECL, CML,
Noninverted Differential Input.
LVCMOS, LVDS,
LVTTL Input
4 VTCLK
.
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