Figure 3. Pin Configuration
Table 2. Pin Descriptions
1 VDD Nominal 3 V supply connection.
2 GND Ground connection. 2
3 RF1 RF port. 1
CMOS or TTL logic level:
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
5 GND Ground connection. 2
6 RF2 RF port. 1
Notes: 1. Both RF pins must be held at 0 VDC or require external DC
2. The exposed pad must be soldered to the ground plane for
proper switch performance.
Table 3. Absolute Maximum Ratings
Power supply voltage
Voltage on CTRL input
Input power (50 Ω),
(Human Body Model)
Min Max Unit
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
Table 4. DC Electrical Specifications
VDD Power Supply
Min Typ Max Unit
2.7 3.0 3.3
IDD Power Supply Current
(VDD = 3V, VCNTL = 3V)
33 40 µA
Control Voltage High
Control Voltage Low
Table 5. Control Logic Truth Table
Control Voltage (CTRL)
Signal Path (RF1 to RF2)
Notes: 1. CTRL accepts both CMOS and TTL voltage levels.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
The PE4232 high isolation SPST CATV Switch is
designed to support CATV applications such as
premise disconnect of a CATV signal path. This
function is typically performed by bulky and
expensive mechanical switches. The high
isolation characteristics, high compression point,
and integrated 75-ohm terminations make the
PE4232 an ideal, cost effective and
manufacturable product of choice.
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of VDD. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the VDD pin when the
control logic input voltage level exceeds VDD.)
Document No. 70-0054-03 │ UltraCMOS™ RFIC Solutions