PLL602-04 - Low Phase Noise CMOS XO

Datasheet Summary

Description

The PLL602-04 is a low cost, high performance and low phase noise XO, providing less than -125 dBc at 10kHz offset in the 96MHz to 200MHz operating range.

Features

PIN.

PhaseLink

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Datasheet Details

Part number	PLL602-04
Manufacturer	PhaseLink
File Size	94.47 KB
Description	Low Phase Noise CMOS XO
Datasheet	PLL602-04 Datasheet
Additional preview pages of the PLL602-04 datasheet.

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Full PDF Text Transcription

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m Preliminary for proposal PLL602-04 o c . Low Phase Noise CMOS XO (96MHz to 200MHz) U t4 e FEATURES PIN CONFIGURATION e h XO for the 96MHz to 200MHz • Low phase noise S range (-125 ta dBc at 10kHz offset). • CMOS a output. • 12 to .D25MHz crystal input. • Integrated crystal load capacitor: no external w load capacitor required. w • Low jitter (RMS): 9-12ps period jitter (1 sigma). w• 3.3V operation. CLK 1 2 3 4 8 7 6 5 GND PLL602-04 VDD OE GND N/C • Available in 8-Pin TSSOP or SOIC. DESCRIPTIONS The PLL602-04 is a low cost, high performance and low phase noise XO, providing less than -125 dBc at 10kHz offset in the 96MHz to 200MHz operating range. The very low jitter (9 to 12 ps RMS period jitter) makes this chip ideal for 155.

Published: Feb 10, 2006 |