PLL650-02 Datasheet PDF - PhaseLink Low EMI Network LAN Clock Specs

PLL650-02 - Low EMI Network LAN Clock

Datasheet Summary

Description

The PLL 650-02 is a low cost, low jitter, and high performance clock synthesizer.

Features

e h.
Full CMOS output swing with 40-mA output drive S output capability. 25-mA drive at TTL level. a t.
Advanced, low power, sub-micron CMOS processes. a.
25MHz . D fundamental crystal or clock input.
4 outputs at 50MHz, 2 outputs selectable at 25MHz or w 125MHz, 1 output selectable at 25MHz or 100MHz. w SDRAM selectable frequencies of 66.6, 75, 83.3, w.
2 100MHz (Double Drive Strength).
PLL6.

Datasheet Details

Part number	PLL650-02
Manufacturer	PhaseLink
File Size	119.99 KB
Description	Low EMI Network LAN Clock
Datasheet	PLL650-02 Datasheet
Additional preview pages of the PLL650-02 datasheet.

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Full PDF Text Transcription

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m o .c U 4 t e FEATURES e h • Full CMOS output swing with 40-mA output drive S output capability. 25-mA drive at TTL level. a t • Advanced, low power, sub-micron CMOS processes. a • 25MHz .D fundamental crystal or clock input. • 4 outputs at 50MHz, 2 outputs selectable at 25MHz or w 125MHz, 1 output selectable at 25MHz or 100MHz. w SDRAM selectable frequencies of 66.6, 75, 83.3, w• 2 100MHz (Double Drive Strength). • • • • • • PLL650-02 Low EMI Network LAN Clock PIN CONFIGURATION VDD XIN XOUT/50MHz_OE*^ GND VDD 1 2 3 4 5 6 7 8 9 24 23 22 21 20 19 18 17 16 15 14 13 VDD VDD 25MHz/100MHz GND SDRAMx2 GND All non SDRAM outputs can be disabled (tri-state) Spread spectrum technology selectable for EMI reduction from ±0.5%, ±0.75% for SDRAM and 100MHz output.

Published: Feb 10, 2006 |