Description
The PLL 650-06 is a low cost, low jitter, and high performance clock synthesizer.
Features
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Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. One output fixed at 50MHz One selectable frequency output of 66.6 or 75MHz (with Double Drive Strength output). Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150m.